Prior art printed circuit boards (PCB) are formed using conductive metal interconnects (known as “traces”) formed on a dielectric substrate, where each surface carrying conductors is known as a “layer”. Each dielectric core has traces formed on one surface or on both surfaces, and by stacking several such dielectric cores having traces formed in them interspersed with bare dielectric layers, and laminating them together under temperature and pressure, a multi-layer printed circuit may be formed. The dielectric substrate comprises an epoxy resin embedded in a fiber matrix such as glass fiber woven into a cloth. In one prior art fabrication method, copper is laminated onto the outer surfaces of a dielectric layer, the copper surfaces are patterned such as with a photoresist or photo sensitive film to create masked and unmasked regions, and then etched to form a conductive trace layer on one or both sides of the core dielectric. A stack of dielectric cores with conductive traces may then be laminated together to form multi-layer boards, and any layer interconnects made with vias, which are drilled holes plated with copper to form annular rings which provide connectivity from one layer to another.
Printed circuit boards (PCB) are typically used to provide conductive traces between various electronic components mounted on the PCB. One type of electronic component is a through-hole device which is mounted on the PCB by having leads positioned through one or more holes in the PCB, where the PCB hole includes a conductive annular ring pad on each trace connect layer, and the component lead is soldered to the annular ring pad of the PCB hole. Through hole components have leads which tend to be difficult to align with the associated PCB mounting hole, but surface mount technology (SMT) provides a preferable mounting system, where component leads are simply placed on the surface of a PCB pad and soldered, which is preferred for PCB assembly because of the higher density and ease of mechanized assembly. Surface mount components require only surface mount pads on an outside finished PCB layer. Within a two layer or multi-layer PCB, interconnects of conductive traces from one layer to another are accomplished using through-hole vias, where a conductive trace on one trace layer leads to a hole which is typically drilled through one or more dielectric layers of the PCB and plated with copper or other conductive metal to complete the trace layer connection. A hole drilled through all dielectric layers is known as a thru-via, a hole drilled through an outer layer only (typically as part of the fabrication of the individual layer) is known as a micro-via, and a hole drilled through one or more inner layers is known as a blind via. For any of these via types, the via is patterned to include an annular ring conductor region on opposite trace layers of the PCB, with the drilled hole lined with conductive material which connects the annular ring conductors on either side of the laminate or PCB.
The thickness of pre-patterned or post-patterned copper on a printed circuit board laminate may be increased using electroplating, where the PCB or dielectric layer with traces is placed in an electrolytic bath, and a DC source is connected between a sacrificial anodic conductor (such as a copper rod) to an existing conductive layer of a PCB. Where a pre-existing conductive copper layer is not present on a PCB to facilitate electroplating, such as the case of bare dielectric material or drilled via holes, a seed layer of copper must first be deposited. This is done using an electroless process with the assistance of a “seed” catalytic material (which enhances the deposition of a particular conductive material) which is deposited on the surface of the dielectric, and the board is then placed in an electroless bath. For a catalyst such as palladium and an electroless bath of copper, the copper ions in solution deposit over the palladium until the surface is covered sufficiently to provide uniform electrical conductivity, after which the copper deposited using the electroless process provides a conductive scaffold for the subsequent addition of material using the electroplating process. Electroplating is preferred for finishing the plating operation, as it has a faster deposition rate than the electroless plating process.
As electronic assemblies increase in complexity, it is desired to increase component densities on PCB assemblies, such as by using smaller trace widths (known as fine pitch traces) in conjunction with increasingly dense integrated circuit (IC) lead patterns. One problem of prior art surface mount PCB fabrication and assembly methods is that because the traces are formed on the surface of the dielectric, the adhesion between copper trace and underlying laminate for narrower conductor line widths (known as fine pitch traces) is reduced, causing the fine pitch traces and component pads to separate (lift) during a component replacement operation, ruining the entire circuit board assembly and expensive components on it. Another problem of fine pitch surface traces is that when fabricating a multi-layer circuit board, the individual trace layers are laminated together under pressure in an elevated temperature environment. During lamination, fine pitch traces tend to migrate laterally across the surface of the dielectric. In high speed circuit design, it is desired to maintain a fixed impedance between traces, particularly for differential pair (edge coupled) transmission lines. This lateral migration of traces during lamination causes the transmission line impedance of the finished PCB differential pair to vary over the length of the trace, which causes reflections and losses in the transmission line compared to one with fixed impedance characteristics resulting from constant spacing.
It is desired to provide a printed circuit board pre-preg and trace forming process which provides trace positions which remain stationary during the lamination process. It is also desired to provide dielectric and trace layers with finished planar surfaces to prevent lateral forces on traces from developing during lamination. It is also desired to provide a catalytic pre-preg for use in printed circuit processing, where the catalytic pre-preg has a catalytic-free surface and where removal of the surface of the catalytic pre-preg exposes the catalytic particles for formation of traces in areas where surface material has been removed.